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<div id="catalog">
<ul>
<li><a href="#Message" style=" font-size: 16px;">Power Messages</a>
</li>
<li><a href="#Summary" style=" font-size: 16px;">Power Summary</a>
<ul>
<li><a href="#Power_Info" style=" font-size: 14px;">Power Information</a></li>
<li><a href="#Thermal_Info" style=" font-size: 14px;">Thermal Information</a></li>
<li><a href="#Configure_Info" style=" font-size: 14px;">Configure Information</a></li>
<li><a href="#Supply_Summary" style=" font-size: 14px;">Supply Information</a></li>
</ul>
</li>
<li><a href="#Detail" style=" font-size: 16px;">Power Details</a>
<ul>
<li><a href="#By_Block_Type" style=" font-size: 14px;">Power By Block Type</a></li>
<li><a href="#By_Hierarchy" style=" font-size: 14px;">Power By Hierarchy</a></li>
<li><a href="#By_Clock_Domain" style=" font-size: 14px;">Power By Clock Domain</a></li>
</ul>
</li>
</ul>
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<div id="content">
<h1><a name="Message">Power Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>Gowin Power Analysis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>C:\Users\hankg\OneDrive\Works\Gowin\Cortex-M3-DualCam\impl\gwsynthesis\gowin_empu_m3.vg</td>
</tr>
<tr>
<td class="label">Physical Constraints File</td>
<td>C:\Users\hankg\OneDrive\Works\Gowin\Cortex-M3-DualCam\src\dual_5640.cst</td>
</tr>
<tr>
<td class="label">Timing Constraints File</td>
<td>---</td>
</tr>
<tr>
<td class="label">GOWIN Version</td>
<td>V1.9.8</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW2A-LV55PG484C8/I7</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW2A-55C</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Mon Nov 29 13:27:58 2021
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2021 Gowin Semiconductor Corporation. All rights reserved.</td>
</tr>
</table>
<h1><a name="Summary">Power Summary</a></h1>
<h2><a name="Power_Info">Power Information:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Total Power (mW)</td>
<td>933.400</td>
</tr>
<tr>
<td class="label">Quiescent Power (mW)</td>
<td>168.579</td>
</tr>
<tr>
<td class="label">Dynamic Power (mW)</td>
<td>764.821</td>
</tr>
</table>
<h2><a name="Thermal_Info">Thermal Information:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Junction Temperature</td>
<td>76.244</td>
</tr>
<tr>
<td class="label">Theta JA</td>
<td>54.900</td>
</tr>
<tr>
<td class="label">Max Allowed Ambient Temperature</td>
<td>33.756</td>
</tr>
</table>
<h2><a name="Configure_Info">Configure Information:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Default IO Toggle Rate</td>
<td>0.125</td>
</tr>
<td class="label">Default Remain Toggle Rate</td>
<td>0.125</td>
</tr>
<tr>
<td class="label">Use Vectorless Estimation</td>
<td>false</td>
</tr>
<tr>
<td class="label">Filter Glitches</td>
<td>false</td>
</tr>
<tr>
<td class="label">Related Vcd File</td>
<td></td>
</tr>
<tr>
<td class="label">Related Saif File</td>
<td></td>
</tr>
<tr>
<td class="label">Use Custom Theta JA</td>
<td>false</td>
</tr>
<tr>
<td class="label">Air Flow</td>
<td>LFM_0</td>
</tr>
<tr>
<td class="label">Heat Sink</td>
<td>None</td>
</tr>
<tr>
<td class="label">Use Custom Theta SA</td>
<td>false</td>
</tr>
<tr>
<td class="label">Board Thermal Model</td>
<td>None</td>
</tr>
<tr>
<td class="label">Use Custom Theta JB</td>
<td>false</td>
</tr>
<tr>
<td class="label">Ambient Temperature</td>
<td>25.000
</tr>
</table>
<h2><a name="Supply_Summary">Supply Information:</a></h2>
<table class="summary_table">
<tr>
<th class="label">Voltage Source</th>
<th class="label">Voltage</th>
<th class="label">Dynamic Current(mA)</th>
<th class="label">Quiescent Current(mA)</th>
<th class="label">Power(mW)</th>
</tr>
<tr>
<td>VCC</td>
<td>1.000</td>
<td>703.936</td>
<td>104.284</td>
<td>808.220</td>
</tr>
<tr>
<td>VCCX</td>
<td>2.500</td>
<td>9.452</td>
<td>23.366</td>
<td>82.043</td>
</tr>
<tr>
<td>VCCO15</td>
<td>1.500</td>
<td>5.512</td>
<td>1.845</td>
<td>11.036</td>
</tr>
<tr>
<td>VCCO25</td>
<td>2.500</td>
<td>7.773</td>
<td>0.185</td>
<td>19.896</td>
</tr>
<tr>
<td>VCCO33</td>
<td>3.300</td>
<td>2.896</td>
<td>0.803</td>
<td>12.205</td>
</tr>
</table>
<h1><a name="Detail">Power Details</a></h1>
<h2><a name="By_Block_Type">Power By Block Type:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Block Type</th>
<th class="label">Total Power(mW)</th>
<th class="label">Static Power(mW)</th>
<th class="label">Average Toggle Rate(millions of transitions/sec)</th>
</tr>
<tr>
<td>Logic</td>
<td>15.254</td>
<td>NA</td>
<td>4.400</td>
</tr>
<tr>
<td>IO</td>
<td>86.667
<td>15.865
<td>26.347
</tr>
<tr>
<td>BSRAM</td>
<td>245.661
<td>NA</td>
<td>NA</td>
</tr>
<tr>
<td>PLL</td>
<td>71.861
<td>NA</td>
<td>NA</td>
</tr>
<tr>
<td>DLL</td>
<td>46.080
<td>NA</td>
<td>NA</td>
</tr>
<tr>
<td>DQS</td>
<td>44.100
<td>NA</td>
<td>NA</td>
</tr>
</table>
<h2><a name="By_Hierarchy">Power By Hierarchy:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Hierarchy Entity</th>
<th class="label">Total Power(mW)</th>
<th class="label">Block Dynamic Power(mW)</th>
</tr>
<tr>
<td>Cortex_M3_DualCam</td>
<td>422.956</td>
<td>422.956(422.956)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/</td>
<td>100.199</td>
<td>100.199(100.199)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/</td>
<td>98.571</td>
<td>98.571(98.569)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/</td>
<td>0.604</td>
<td>0.604(0.604)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/</td>
<td>0.604</td>
<td>0.604(0.604)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_ahb10/</td>
<td>0.001</td>
<td>0.001(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_ahb11/</td>
<td>0.001</td>
<td>0.001(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_ahb12/</td>
<td>0.001</td>
<td>0.001(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_ahb4/</td>
<td>0.001</td>
<td>0.001(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_ahb5/</td>
<td>0.001</td>
<td>0.001(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_ahb6/</td>
<td>0.001</td>
<td>0.001(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_ahb7/</td>
<td>0.001</td>
<td>0.001(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_ahb8/</td>
<td>0.001</td>
<td>0.001(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_ahb9/</td>
<td>0.001</td>
<td>0.001(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_ahb_ahbext/</td>
<td>0.001</td>
<td>0.001(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_ahb_apb2/</td>
<td>0.001</td>
<td>0.001(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_ahb_can/</td>
<td>0.001</td>
<td>0.001(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_ahb_internet/</td>
<td>0.001</td>
<td>0.001(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_cmsdk_ahb_gpio_0/</td>
<td>0.080</td>
<td>0.080(0.080)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_cmsdk_ahb_gpio_0/u_ahb_to_gpio/</td>
<td>0.002</td>
<td>0.002(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_cmsdk_ahb_gpio_0/u_iop_gpio/</td>
<td>0.078</td>
<td>0.078(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_gowinahbext/</td>
<td>0.067</td>
<td>0.067(0.067)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_gowinahbext/u_bus_matrix/</td>
<td>0.067</td>
<td>0.067(0.067)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_gowinahbext/u_bus_matrix/uInputStage0/</td>
<td>0.006</td>
<td>0.006(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_gowinahbext/u_bus_matrix/uMatrixDecodeS0/</td>
<td>0.009</td>
<td>0.009(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage0/</td>
<td>0.005</td>
<td>0.005(0.001)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage0/uOutputArb/</td>
<td>0.001</td>
<td>0.001(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage1/</td>
<td>0.003</td>
<td>0.003(0.001)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage1/uOutputArb/</td>
<td>0.001</td>
<td>0.001(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage10/</td>
<td>0.002</td>
<td>0.002(0.001)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage10/uOutputArb/</td>
<td>0.001</td>
<td>0.001(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage11/</td>
<td>0.002</td>
<td>0.002(0.001)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage11/uOutputArb/</td>
<td>0.001</td>
<td>0.001(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage12/</td>
<td>0.002</td>
<td>0.002(0.001)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage12/uOutputArb/</td>
<td>0.001</td>
<td>0.001(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage13/</td>
<td>0.002</td>
<td>0.002(0.001)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage13/uOutputArb/</td>
<td>0.001</td>
<td>0.001(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage14/</td>
<td>0.002</td>
<td>0.002(0.001)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage14/uOutputArb/</td>
<td>0.001</td>
<td>0.001(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage15/</td>
<td>0.002</td>
<td>0.002(0.001)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage15/uOutputArb/</td>
<td>0.001</td>
<td>0.001(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage2/</td>
<td>0.003</td>
<td>0.003(0.001)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage2/uOutputArb/</td>
<td>0.001</td>
<td>0.001(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage3/</td>
<td>0.010</td>
<td>0.010(0.001)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage3/uOutputArb/</td>
<td>0.001</td>
<td>0.001(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage4/</td>
<td>0.006</td>
<td>0.006(0.001)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage4/uOutputArb/</td>
<td>0.001</td>
<td>0.001(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage5/</td>
<td>0.003</td>
<td>0.003(0.001)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage5/uOutputArb/</td>
<td>0.001</td>
<td>0.001(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage6/</td>
<td>0.003</td>
<td>0.003(0.001)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage6/uOutputArb/</td>
<td>0.001</td>
<td>0.001(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage7/</td>
<td>0.002</td>
<td>0.002(0.001)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage7/uOutputArb/</td>
<td>0.001</td>
<td>0.001(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage8/</td>
<td>0.004</td>
<td>0.004(0.001)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage8/uOutputArb/</td>
<td>0.001</td>
<td>0.001(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage9/</td>
<td>0.002</td>
<td>0.002(0.001)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage9/uOutputArb/</td>
<td>0.001</td>
<td>0.001(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_gw_apb_int_wrapper/</td>
<td>0.088</td>
<td>0.088(0.088)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/</td>
<td>0.067</td>
<td>0.067(0.067)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/</td>
<td>0.067</td>
<td>0.067(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_gw_apb_int_wrapper/u_p_sse050_interconnect_f0_ahb_to_apb/</td>
<td>0.021</td>
<td>0.021(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_spi1/</td>
<td>0.360</td>
<td>0.360(0.360)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_spi1/u_spi_ahbif_ctrl/</td>
<td>0.078</td>
<td>0.078(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_spi1/u_spi_arbiter/</td>
<td>0.005</td>
<td>0.005(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_spi1/u_spi_ctrl/</td>
<td>0.126</td>
<td>0.126(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_spi1/u_spi_fifo/</td>
<td>0.033</td>
<td>0.033(0.032)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_spi1/u_spi_fifo/rxf_clr_ack_sync/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_spi1/u_spi_fifo/rxf_clr_sync/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_spi1/u_spi_fifo/txf_clr_ack_sync/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_spi1/u_spi_fifo/txf_clr_sync/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_spi1/u_spi_fifo/u_spi_rxfifo/</td>
<td>0.021</td>
<td>0.021(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_spi1/u_spi_fifo/u_spi_txfifo/</td>
<td>0.010</td>
<td>0.010(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_spi1/u_spi_reg/</td>
<td>0.073</td>
<td>0.073(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_spi1/u_spi_regif/</td>
<td>0.002</td>
<td>0.002(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_spi1/u_spi_spiif/</td>
<td>0.037</td>
<td>0.037(0.001)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_spi1/u_spi_spiif/spi_clk_in_syn/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_spi1/u_spi_spiif/spi_cs_n_syn/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_spi1/u_spi_sync/</td>
<td>0.006</td>
<td>0.006(0.006)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_spi1/u_spi_sync/arb_addr_latched_sync/</td>
<td>0.001</td>
<td>0.001(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_spi1/u_spi_sync/arb_busy_sync/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_spi1/u_spi_sync/arb_mem_req_sync/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_spi1/u_spi_sync/arb_req_sync/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_spi1/u_spi_sync/arb_trans_end_sync/</td>
<td>0.001</td>
<td>0.001(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_spi1/u_spi_sync/mem_intf_idle_clr_sync/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_spi1/u_spi_sync/rxf_overrun_sync/</td>
<td>0.001</td>
<td>0.001(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_spi1/u_spi_sync/slave_cmd_wr_sync/</td>
<td>0.001</td>
<td>0.001(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_spi1/u_spi_sync/slave_rcnt_inc_sync/</td>
<td>0.001</td>
<td>0.001(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_spi1/u_spi_sync/slave_wcnt_inc_sync/</td>
<td>0.001</td>
<td>0.001(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_spi1/u_spi_sync/spi_reset_ack_sync/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_spi1/u_spi_sync/spi_reset_sync/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_spi1/u_spi_sync/txf_underrun_sync/</td>
<td>0.001</td>
<td>0.001(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/</td>
<td>97.965</td>
<td>97.965(97.965)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/</td>
<td>6.770</td>
<td>6.770(6.751)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/</td>
<td>5.763</td>
<td>5.763(5.763)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_bus_matrix/</td>
<td>0.583</td>
<td>0.583(0.583)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_bus_matrix/u_cm3_mtx_bit_master/</td>
<td>0.122</td>
<td>0.122(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_bus_matrix/u_cm3_mtx_decode_dap/</td>
<td>0.003</td>
<td>0.003(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_bus_matrix/u_cm3_mtx_decode_dcore/</td>
<td>0.137</td>
<td>0.137(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_bus_matrix/u_cm3_mtx_decode_icore/</td>
<td>0.063</td>
<td>0.063(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_bus_matrix/u_cm3_mtx_input_stage_dap/</td>
<td>0.001</td>
<td>0.001(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_bus_matrix/u_cm3_mtx_input_stage_dcore/</td>
<td>0.008</td>
<td>0.008(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_bus_matrix/u_cm3_mtx_input_stage_icore/</td>
<td>0.005</td>
<td>0.005(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_bus_matrix/u_cm3_mtx_output_stage_dcode/</td>
<td>0.151</td>
<td>0.151(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_bus_matrix/u_cm3_mtx_output_stage_icode/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_bus_matrix/u_cm3_mtx_output_stage_ppb/</td>
<td>0.038</td>
<td>0.038(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_bus_matrix/u_cm3_mtx_output_stage_sys/</td>
<td>0.054</td>
<td>0.054(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/</td>
<td>0.163</td>
<td>0.163(0.163)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_mst/</td>
<td>0.089</td>
<td>0.089(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/</td>
<td>0.074</td>
<td>0.074(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_sync_end_trans/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_sync_habort/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_sync_htrans/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_sync_idle/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_sync_tra/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_sync_trans_rtn/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/</td>
<td>3.147</td>
<td>3.147(3.147)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/</td>
<td>0.962</td>
<td>0.962(0.962)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_ctl/</td>
<td>0.079</td>
<td>0.079(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/</td>
<td>0.883</td>
<td>0.883(0.317)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/u_cm3_dpu_alu_srtdiv/</td>
<td>0.317</td>
<td>0.317(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_dec/</td>
<td>0.264</td>
<td>0.264(0.047)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_dec/u_cm3_dpu_32bit_dec/</td>
<td>0.005</td>
<td>0.005(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_dec/u_cm3_dpu_br_dec/</td>
<td>0.041</td>
<td>0.041(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_etmintf/</td>
<td>0.054</td>
<td>0.054(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_exec/</td>
<td>0.118</td>
<td>0.118(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_fetch/</td>
<td>0.372</td>
<td>0.372(0.372)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_fetch/u_cm3_dpu_fetch_ahbintf/</td>
<td>0.362</td>
<td>0.362(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_fetch/u_cm3_dpu_fetch_ctl/</td>
<td>0.010</td>
<td>0.010(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/</td>
<td>0.679</td>
<td>0.679(0.679)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ahbintf/</td>
<td>0.541</td>
<td>0.541(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/</td>
<td>0.138</td>
<td>0.138(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/</td>
<td>0.572</td>
<td>0.572(0.158)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/u_cm3_dpu_regfile/</td>
<td>0.158</td>
<td>0.158(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/</td>
<td>0.127</td>
<td>0.127(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dwt/</td>
<td>0.429</td>
<td>0.429(0.429)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dwt/u_cm3_dwt_comp0/</td>
<td>0.055</td>
<td>0.055(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dwt/u_cm3_dwt_comp1/</td>
<td>0.135</td>
<td>0.135(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dwt/u_cm3_dwt_comp2/</td>
<td>0.045</td>
<td>0.045(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dwt/u_cm3_dwt_comp3/</td>
<td>0.045</td>
<td>0.045(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dwt/u_cm3_dwt_packet_gen/</td>
<td>0.058</td>
<td>0.058(0.005)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dwt/u_cm3_dwt_packet_gen/u_dwt_state_data/</td>
<td>0.001</td>
<td>0.001(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dwt/u_cm3_dwt_packet_gen/u_dwt_state_events/</td>
<td>0.001</td>
<td>0.001(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dwt/u_cm3_dwt_packet_gen/u_dwt_state_int_trace/</td>
<td>0.001</td>
<td>0.001(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dwt/u_cm3_dwt_packet_gen/u_dwt_state_pc_periodic/</td>
<td>0.001</td>
<td>0.001(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dwt/u_cm3_dwt_packet_gen/u_dwt_state_pc_sample/</td>
<td>0.001</td>
<td>0.001(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dwt/u_dwt_apb_if/</td>
<td>0.090</td>
<td>0.090(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_fpb/</td>
<td>0.089</td>
<td>0.089(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_itm/</td>
<td>0.175</td>
<td>0.175(0.175)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_itm/u_itm_arb/</td>
<td>0.002</td>
<td>0.002(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_itm/u_itm_emit/</td>
<td>0.012</td>
<td>0.012(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_itm/u_itm_fifo/</td>
<td>0.107</td>
<td>0.107(0.035)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_itm/u_itm_fifo/u_itm_fifo_byte_0/</td>
<td>0.007</td>
<td>0.007(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_itm/u_itm_fifo/u_itm_fifo_byte_1/</td>
<td>0.007</td>
<td>0.007(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_itm/u_itm_fifo/u_itm_fifo_byte_2/</td>
<td>0.007</td>
<td>0.007(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_itm/u_itm_fifo/u_itm_fifo_byte_3/</td>
<td>0.007</td>
<td>0.007(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_itm/u_itm_fifo/u_itm_fifo_byte_4/</td>
<td>0.007</td>
<td>0.007(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_itm/u_itm_if/</td>
<td>0.028</td>
<td>0.028(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_itm/u_itm_ts/</td>
<td>0.025</td>
<td>0.025(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_mpu/</td>
<td>0.485</td>
<td>0.485(0.485)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_mpu/u_cm3_mpu_full/</td>
<td>0.485</td>
<td>0.485(0.485)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_mpu/u_cm3_mpu_full/u_cm3_mpu_ahb_ctl/</td>
<td>0.048</td>
<td>0.048(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_mpu/u_cm3_mpu_full/u_cm3_mpu_align/</td>
<td>0.055</td>
<td>0.055(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_mpu/u_cm3_mpu_full/u_cm3_mpu_ppb_intf/</td>
<td>0.010</td>
<td>0.010(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_mpu/u_cm3_mpu_full/u_cm3_mpu_regions/</td>
<td>0.373</td>
<td>0.373(0.231)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_mpu/u_cm3_mpu_full/u_cm3_mpu_regions/u_cm3_mpu_region_0/</td>
<td>0.008</td>
<td>0.008(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_mpu/u_cm3_mpu_full/u_cm3_mpu_regions/u_cm3_mpu_region_1/</td>
<td>0.052</td>
<td>0.052(0.045)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_mpu/u_cm3_mpu_full/u_cm3_mpu_regions/u_cm3_mpu_region_1/u_cm3_mpu_dcomp/</td>
<td>0.019</td>
<td>0.019(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_mpu/u_cm3_mpu_full/u_cm3_mpu_regions/u_cm3_mpu_region_1/u_cm3_mpu_icomp/</td>
<td>0.026</td>
<td>0.026(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_mpu/u_cm3_mpu_full/u_cm3_mpu_regions/u_cm3_mpu_region_2/</td>
<td>0.007</td>
<td>0.007(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_mpu/u_cm3_mpu_full/u_cm3_mpu_regions/u_cm3_mpu_region_3/</td>
<td>0.049</td>
<td>0.049(0.042)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_mpu/u_cm3_mpu_full/u_cm3_mpu_regions/u_cm3_mpu_region_3/u_cm3_mpu_dcomp/</td>
<td>0.017</td>
<td>0.017(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_mpu/u_cm3_mpu_full/u_cm3_mpu_regions/u_cm3_mpu_region_3/u_cm3_mpu_icomp/</td>
<td>0.025</td>
<td>0.025(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_mpu/u_cm3_mpu_full/u_cm3_mpu_regions/u_cm3_mpu_region_4/</td>
<td>0.007</td>
<td>0.007(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_mpu/u_cm3_mpu_full/u_cm3_mpu_regions/u_cm3_mpu_region_5/</td>
<td>0.049</td>
<td>0.049(0.042)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_mpu/u_cm3_mpu_full/u_cm3_mpu_regions/u_cm3_mpu_region_5/u_cm3_mpu_dcomp/</td>
<td>0.017</td>
<td>0.017(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_mpu/u_cm3_mpu_full/u_cm3_mpu_regions/u_cm3_mpu_region_5/u_cm3_mpu_icomp/</td>
<td>0.025</td>
<td>0.025(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_mpu/u_cm3_mpu_full/u_cm3_mpu_regions/u_cm3_mpu_region_6/</td>
<td>0.007</td>
<td>0.007(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_mpu/u_cm3_mpu_full/u_cm3_mpu_regions/u_cm3_mpu_region_7/</td>
<td>0.051</td>
<td>0.051(0.044)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_mpu/u_cm3_mpu_full/u_cm3_mpu_regions/u_cm3_mpu_region_7/u_cm3_mpu_dcomp/</td>
<td>0.017</td>
<td>0.017(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_mpu/u_cm3_mpu_full/u_cm3_mpu_regions/u_cm3_mpu_region_7/u_cm3_mpu_icomp/</td>
<td>0.026</td>
<td>0.026(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_nvic/</td>
<td>0.683</td>
<td>0.683(0.683)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_nvic/u_cm3_nvic_main/</td>
<td>0.443</td>
<td>0.443(0.286)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_nvic/u_cm3_nvic_main/u_cm3_nvic_int_state/</td>
<td>0.159</td>
<td>0.159(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_nvic/u_cm3_nvic_main/u_cm3_nvic_pend_tree/</td>
<td>0.127</td>
<td>0.127(0.127)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_nvic/u_cm3_nvic_main/u_cm3_nvic_pend_tree/u_cell__63_to___0/</td>
<td>0.127</td>
<td>0.127(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_nvic/u_cm3_nvic_ppb_intf/</td>
<td>0.006</td>
<td>0.006(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_nvic/u_cm3_nvic_reg/</td>
<td>0.234</td>
<td>0.234(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_ppb_ahb_to_apb/</td>
<td>0.003</td>
<td>0.003(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_ppb_decoder/</td>
<td>0.006</td>
<td>0.006(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_sync_dbg_en/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/</td>
<td>0.916</td>
<td>0.916(0.916)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/</td>
<td>0.192</td>
<td>0.192(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbSync/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbSync/uSyncBusAbort/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbSync/uSyncBusReq/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpIMux/</td>
<td>0.043</td>
<td>0.043(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPJtagDpProtocol/</td>
<td>0.229</td>
<td>0.229(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwDpProtocol/</td>
<td>0.401</td>
<td>0.401(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwDpSync/</td>
<td>0.003</td>
<td>0.003(0.003)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwDpSync/uCDBGPWRUPACK/</td>
<td>0.001</td>
<td>0.001(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwDpSync/uCSYSPWRUPACK/</td>
<td>0.001</td>
<td>0.001(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwDpSync/uSyncBusAck/</td>
<td>0.001</td>
<td>0.001(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/</td>
<td>0.049</td>
<td>0.049(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/u_cm3_rom_table/</td>
<td>0.002</td>
<td>0.002(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/u_cm3_sync_dappwrup/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/u_cm3_sync_dbgen/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/u_cm3_sync_hclken/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/u_cm3_tpiu/</td>
<td>0.069</td>
<td>0.069(0.069)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/u_cm3_tpiu/u_cm3_tpiu_apb_if/</td>
<td>0.011</td>
<td>0.011(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/u_cm3_tpiu/u_cm3_tpiu_atb_fifo1/</td>
<td>0.010</td>
<td>0.010(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/u_cm3_tpiu/u_cm3_tpiu_atb_sync/</td>
<td>0.001</td>
<td>0.001(0.001)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/u_cm3_tpiu/u_cm3_tpiu_atb_sync/u_read_pointer1_gray0/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/u_cm3_tpiu/u_cm3_tpiu_atb_sync/u_read_pointer1_gray1/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/u_cm3_tpiu/u_cm3_tpiu_atb_sync/u_read_pointer1_gray2/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/u_cm3_tpiu/u_cm3_tpiu_atb_sync/u_sync_ack_async/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/u_cm3_tpiu/u_cm3_tpiu_atb_sync/u_tpiu_baud/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/u_cm3_tpiu/u_cm3_tpiu_atb_sync/u_trace_out_idle/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/u_cm3_tpiu/u_cm3_tpiu_trace_fifo1/</td>
<td>0.004</td>
<td>0.004(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/u_cm3_tpiu/u_cm3_tpiu_trace_out/</td>
<td>0.025</td>
<td>0.025(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/u_cm3_tpiu/u_cm3_tpiu_trace_sync/</td>
<td>0.001</td>
<td>0.001(0.001)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/u_cm3_tpiu/u_cm3_tpiu_trace_sync/u_baud_div_reset/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/u_cm3_tpiu/u_cm3_tpiu_trace_sync/u_sync_valid_async/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/u_cm3_tpiu/u_cm3_tpiu_trace_sync/u_write_pointer1_gray0/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/u_cm3_tpiu/u_cm3_tpiu_trace_sync/u_write_pointer1_gray1/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/u_cm3_tpiu/u_cm3_tpiu_trace_sync/u_write_pointer1_gray2/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/u_cm3_tpiu/u_tpiu_formatter/</td>
<td>0.017</td>
<td>0.017(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/u_ahb_s_mux/</td>
<td>0.001</td>
<td>0.001(0.001)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/u_ahb_s_mux/u_ahb_decoder/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/u_ahb_s_mux/u_ahb_mux/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/u_ahb_to_ram/</td>
<td>0.028</td>
<td>0.028(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/u_ahb_to_rom/</td>
<td>0.030</td>
<td>0.030(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/u_dtcm/</td>
<td>7.027</td>
<td>7.027(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/u_itcm/</td>
<td>84.097</td>
<td>84.097(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/ucm3_code_mux/</td>
<td>0.011</td>
<td>0.011(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/Cortex_M3/u_Gowin_rPLL/</td>
<td>1.628</td>
<td>1.628(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/</td>
<td>322.757</td>
<td>322.757(322.756)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/DDR3_MIG/</td>
<td>157.229</td>
<td>157.229(157.229)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/DDR3_MIG/gw3_top/</td>
<td>157.229</td>
<td>157.229(157.229)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/DDR3_MIG/gw3_top/i4/</td>
<td>156.467</td>
<td>156.467(110.197)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/DDR3_MIG/gw3_top/i4/ddr3_sync/</td>
<td>0.045</td>
<td>0.045(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/</td>
<td>0.302</td>
<td>0.302(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/</td>
<td>109.850</td>
<td>109.850(109.846)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/</td>
<td>87.577</td>
<td>87.577(87.573)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/</td>
<td>22.052</td>
<td>22.052(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_in_fifo/</td>
<td>32.760</td>
<td>32.760(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_out_fifo/</td>
<td>32.760</td>
<td>32.760(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/</td>
<td>22.055</td>
<td>22.055(22.050)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/</td>
<td>22.050</td>
<td>22.050(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/</td>
<td>0.109</td>
<td>0.109(0.077)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_cmd_fifo/</td>
<td>0.077</td>
<td>0.077(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/u_fifo_ctrl/</td>
<td>0.105</td>
<td>0.105(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/DDR3_MIG/gw3_top/u_gwmc_top/</td>
<td>0.762</td>
<td>0.762(0.632)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/DDR3_MIG/gw3_top/u_gwmc_top/gw_cmd0/</td>
<td>0.160</td>
<td>0.160(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/DDR3_MIG/gw3_top/u_gwmc_top/gw_rd_data0/</td>
<td>0.097</td>
<td>0.097(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/DDR3_MIG/gw3_top/u_gwmc_top/gw_wr_data0/</td>
<td>0.137</td>
<td>0.137(0.136)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/DDR3_MIG/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/</td>
<td>0.136</td>
<td>0.136(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/DDR3_MIG/gw3_top/u_gwmc_top/gwmc_bank_ctrl/</td>
<td>0.178</td>
<td>0.178(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/DDR3_MIG/gw3_top/u_gwmc_top/gwmc_rank_ctrl/</td>
<td>0.043</td>
<td>0.043(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/DDR3_MIG/gw3_top/u_gwmc_top/gwmc_timing_ctrl/</td>
<td>0.016</td>
<td>0.016(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/DVI_TX/</td>
<td>0.542</td>
<td>0.542(0.542)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/DVI_TX/rgb2dvi_inst/</td>
<td>0.542</td>
<td>0.542(0.542)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/DVI_TX/rgb2dvi_inst/TMDS8b10b_inst_b/</td>
<td>0.180</td>
<td>0.180(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/DVI_TX/rgb2dvi_inst/TMDS8b10b_inst_g/</td>
<td>0.183</td>
<td>0.183(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/DVI_TX/rgb2dvi_inst/TMDS8b10b_inst_r/</td>
<td>0.180</td>
<td>0.180(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/Video_Frame_Buffer/</td>
<td>87.014</td>
<td>87.014(87.014)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/</td>
<td>87.014</td>
<td>87.014(87.014)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/</td>
<td>86.867</td>
<td>86.867(86.867)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/</td>
<td>0.010</td>
<td>0.010(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/</td>
<td>41.121</td>
<td>41.121(41.059)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/</td>
<td>41.007</td>
<td>41.007(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/</td>
<td>0.052</td>
<td>0.052(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/</td>
<td>45.736</td>
<td>45.736(45.683)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/</td>
<td>45.621</td>
<td>45.621(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_16b_32b/</td>
<td>0.062</td>
<td>0.062(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u_dma_bus_arbiter/</td>
<td>0.147</td>
<td>0.147(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/pll_ddr3/</td>
<td>20.920</td>
<td>20.920(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/syn_gen_inst/</td>
<td>0.064</td>
<td>0.064(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/u0_ov5640_dri/</td>
<td>1.789</td>
<td>1.789(1.789)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/u0_ov5640_dri/u_cmos_capture_data/</td>
<td>0.045</td>
<td>0.045(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/u0_ov5640_dri/u_i2c_cfg/</td>
<td>1.617</td>
<td>1.617(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/u0_ov5640_dri/u_i2c_dr/</td>
<td>0.127</td>
<td>0.127(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/u1_ov5640_dri/</td>
<td>1.785</td>
<td>1.785(1.785)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/u1_ov5640_dri/u_cmos_capture_data/</td>
<td>0.041</td>
<td>0.041(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/u1_ov5640_dri/u_i2c_cfg/</td>
<td>1.617</td>
<td>1.617(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/u1_ov5640_dri/u_i2c_dr/</td>
<td>0.128</td>
<td>0.128(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/u_cmos_add/</td>
<td>4.100</td>
<td>4.100(3.892)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/u_cmos_add/u_fifo_pong/</td>
<td>1.946</td>
<td>1.946(1.946)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/u_cmos_add/u_fifo_pong/fifo_inst/</td>
<td>1.946</td>
<td>1.946(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/u_cmos_add/u_fifo_splicing/</td>
<td>1.946</td>
<td>1.946(1.946)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/u_cmos_add/u_fifo_splicing/fifo_inst/</td>
<td>1.946</td>
<td>1.946(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/u_cmos_rpll/</td>
<td>10.460</td>
<td>10.460(0.000)</td>
<tr>
<td>Cortex_M3_DualCam/graphics_processing_unit/u_tmds_pll/</td>
<td>38.852</td>
<td>38.852(0.000)</td>
</table>
<h2><a name="By_Clock_Domain">Power By Clock Domain:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Domain</th>
<th class="label">Clock Frequency(Mhz)</th>
<th class="label">Total Dynamic Power(mW)</th>
</tr>
<tr>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk</td>
<td>20.000</td>
<td>128.477</td>
</tr>
<tr>
<td>SWCLK</td>
<td>100.000</td>
<td>30.784</td>
</tr>
<tr>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_spi1/u_spi_spiif/n344_6</td>
<td>100.000</td>
<td>11.503</td>
</tr>
<tr>
<td>cam0_pclk</td>
<td>100.000</td>
<td>92.304</td>
</tr>
<tr>
<td>graphics_processing_unit/u0_ov5640_dri/dri_clk_2</td>
<td>100.000</td>
<td>22.337</td>
</tr>
<tr>
<td>graphics_processing_unit/u_cmos_rpll/rpll_inst/CLKOUT.default_gen_clk</td>
<td>100.000</td>
<td>17.581</td>
</tr>
<tr>
<td>NO CLOCK DOMAIN</td>
<td>0.000</td>
<td>44.100</td>
</tr>
<tr>
<td>graphics_processing_unit/u1_ov5640_dri/dri_clk_2</td>
<td>100.000</td>
<td>22.337</td>
</tr>
<tr>
<td>cam1_pclk</td>
<td>100.000</td>
<td>25.609</td>
</tr>
<tr>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
<td>50.000</td>
<td>145.757</td>
</tr>
<tr>
<td>cam0_vsync</td>
<td>100.000</td>
<td>11.497</td>
</tr>
<tr>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk</td>
<td>74.286</td>
<td>45.692</td>
</tr>
<tr>
<td>sys_clk</td>
<td>50.000</td>
<td>82.580</td>
</tr>
<tr>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst</td>
<td>100.000</td>
<td>11.480</td>
</tr>
<tr>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk</td>
<td>200.000</td>
<td>46.080</td>
</tr>
</table>
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